SystemVerilog for Design [electronic resource] : A Guide to Using SystemVerilog for Hardware Design and Modeling / by Stuart Sutherland, Simon Davidmann, Peter Flake.Material type: TextLanguage: English Publisher: Boston, MA : Springer US, 2006Edition: Second EditionDescription: XXX, 418 p. online resourceContent type: text Media type: computer Carrier type: online resourceISBN: 9780387364957Subject(s): Engineering | Computer hardware | Computer aided design | Systems engineering | Engineering | Circuits and Systems | Computer-Aided Engineering (CAD, CAE) and Design | Computer Hardware | Electronic and Computer EngineeringAdditional physical formats: Printed edition:: No titleDDC classification: 621.3815 LOC classification: TK7888.4Online resources: Click here to access online
to SystemVerilog -- SystemVerilog Declaration Spaces -- SystemVerilog Literal Values and Built-in Data Types -- SystemVerilog User-Defined and Enumerated Types -- SystemVerilog Arrays, Structures and Unions -- SystemVerilog Procedural Blocks, Tasks and Functions -- SystemVerilog Procedural Statements -- Modeling Finite State Machines with SystemVerilog -- SystemVerilog Design Hierarchy -- SystemVerilog Interfaces -- A Complete Design Modeled with SystemVerilog -- Behavioral and Transaction Level Modeling.
SystemVerilog is a rich set of extensions to the Verilog Hardware Description Language (Verilog HDL). SystemVerilog for Design describes the correct usage of these extensions for modeling digital designs. These important extensions enable the representation of complex digital logic in concise, accurate, and reusable hardware models. All key SystemVerilog design features are presented, such as declaration spaces, two-state data types, enumerated types, user-defined types, structures, unions, interfaces, and RTL coding extensions. Emphasis is placed on the proper usage of these enhancements for simulation and synthesis. Design engineers, engineering managers and engineering students working with all sizes and types of digital designs, whether FPGA, ASIC or full custom, will find this book to be an invaluable learning tool and reference guide. The second edition of this book reflects the official IEEE 1800-2005 SystemVerilog standard. This IEEE SystemVerilog standard adds new capabilities, clarifications, and changes to the Accellera 3.1 SystemVerilog upon which the first edition of this book was based. Significant updates and revisions in the new edition include: A new chapter showing how to use SystemVerilog packages with single-file and multi-file compilers. - New code examples illustrating correct usage of the IEEE version of SystemVerilog. - Updated coding guidelines reflecting the capabilities of current simulator and synthesis Electronic Design Automation tools such as digital simulators and synthesis compilers. "SystemVerilog makes it easier to produce more efficient and concise descriptions of complex hardware designs. The authors of this book have been involved with the development of the language from the beginning, and who is better to learn from than those involved from day one?" — Greg Spirakis, Vice President of Design Technology Intel Corporation "Sun has been a driving force in SystemVerilog from its inception. SystemVerilog can significantly improve the productivity of designers in the coming years, and this book is a comprehensive reference text for engineers who want to learn about SystemVerilog for their next generation designs." — Sunil Joshi, Vice President of Software Technologies & Compute Resources Sun Microsystems, Inc. "SystemVerilog addresses the need for efficient and powerful modeling essential to support the complexity, size and scale of next generation hardware designs. This book explains how to use SystemVerilog effectively and provides numerous examples to illustrate how each of the language constructs can best be utilized." — Chris Malachowsky, Co-Founder and Vice President of Hardware NVIDIA Corp.