Interconnect Noise Optimization in Nanometer Technologies [electronic resource] / by Mohamed A. Elgamel, Magdy A. Bayoumi.

By: Elgamel, Mohamed A [author.]Contributor(s): Bayoumi, Magdy A [author.] | SpringerLink (Online service)Material type: TextTextLanguage: English Publisher: Boston, MA : Springer US, 2006Description: XIX, 137 p. online resourceContent type: text Media type: computer Carrier type: online resourceISBN: 9780387293660Subject(s): Engineering | Computer hardware | Computer aided design | Systems engineering | Engineering | Circuits and Systems | Computer-Aided Engineering (CAD, CAE) and Design | Computer Hardware | Electronic and Computer EngineeringAdditional physical formats: Printed edition:: No titleDDC classification: 621.3815 LOC classification: TK7888.4Online resources: Click here to access online
Contents:
Noise Analysis and Design in Deep Submicron -- Interconnect Noise Analysis and Optimization Techniques -- Crosstalk Noise Analysis in Ultra Deep Submicrometer Technologies -- Minimum Area Shield Insertion for Inductive Noise Reduction -- Spacing Algorithms for Crosstalk Noise Reduction -- Post Layout Interconnect Optimization for Crosscoupling Noise Reduction -- 3D Integration -- EDA Industry Tools: State of the ART.
In: Springer eBooksSummary: Interconnect has become the dominating factor in determining system performance in nanometer technologies. Dedicated to this subject, Interconnect Noise Optimization in Nanometer Technologies provides insight and intuition into layout analysis and optimization for interconnect in high speed, high complexity integrated circuits. The authors bring together a wealth of information presenting a range of CAD algorithms and techniques for synthesizing and optimizing interconnect. Practical aspects of the algorithms and the models are explained with sufficient details. The book investigates the most effective parameters in layout optimization. Different post-layout optimization techniques with complexity analysis and benchmarks tests are provided. The impact crosstalk noise and coupling on the wire delay is analyzed. Parameters that affect signal integrity are also considered.
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Noise Analysis and Design in Deep Submicron -- Interconnect Noise Analysis and Optimization Techniques -- Crosstalk Noise Analysis in Ultra Deep Submicrometer Technologies -- Minimum Area Shield Insertion for Inductive Noise Reduction -- Spacing Algorithms for Crosstalk Noise Reduction -- Post Layout Interconnect Optimization for Crosscoupling Noise Reduction -- 3D Integration -- EDA Industry Tools: State of the ART.

Interconnect has become the dominating factor in determining system performance in nanometer technologies. Dedicated to this subject, Interconnect Noise Optimization in Nanometer Technologies provides insight and intuition into layout analysis and optimization for interconnect in high speed, high complexity integrated circuits. The authors bring together a wealth of information presenting a range of CAD algorithms and techniques for synthesizing and optimizing interconnect. Practical aspects of the algorithms and the models are explained with sufficient details. The book investigates the most effective parameters in layout optimization. Different post-layout optimization techniques with complexity analysis and benchmarks tests are provided. The impact crosstalk noise and coupling on the wire delay is analyzed. Parameters that affect signal integrity are also considered.

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