Variation Tolerant On-Chip Interconnects [electronic resource] / by Ethiopia Enideg Nigussie.

By: Nigussie, Ethiopia Enideg [author.]Contributor(s): SpringerLink (Online service)Material type: TextTextLanguage: English Series: Analog Circuits and Signal Processing: Publisher: New York, NY : Springer New York, 2012Description: XII, 172 p. online resourceContent type: text Media type: computer Carrier type: online resourceISBN: 9781461401315Subject(s): Engineering | Electronics | Systems engineering | Engineering | Circuits and Systems | Electronics and Microelectronics, Instrumentation | Nanotechnology and MicroengineeringAdditional physical formats: Printed edition:: No titleDDC classification: 621.3815 LOC classification: TK7888.4Online resources: Click here to access online
Contents:
Introduction -- On-Chip Communication -- Interconnect Design Techniques -- Design of Delay-Insensitive Current Sensing Interconnects -- Enhancing Completion Detection Performance -- Energy Efficient Semi-Serial Interconnect -- Comparison of the Designed Interconnects -- Circuit Techniques for PVT Variation Tolerance.
In: Springer eBooksSummary: This book presents design techniques, analysis and implementation of high performance and power efficient, variation tolerant on-chip interconnects.  Given the design paradigm shift to multi-core, interconnect-centric designs and the increase in sources of variability and their impact in sub-100nm technologies, this book will be an invaluable reference for anyone concerned with the design of next generation, high-performance electronics systems. Provides comprehensive, circuit-level explanation of high-performance, energy-efficient, variation-tolerant on-chip interconnect; Describes design techniques to mitigate problems caused by variation; Includes techniques for design and implementation of self-timed on-chip interconnect, delay variation insensitive communication protocols, high speed signaling techniques and circuits, bit-width independent completion detection and process, voltage and temperature variation tolerance.                          
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Introduction -- On-Chip Communication -- Interconnect Design Techniques -- Design of Delay-Insensitive Current Sensing Interconnects -- Enhancing Completion Detection Performance -- Energy Efficient Semi-Serial Interconnect -- Comparison of the Designed Interconnects -- Circuit Techniques for PVT Variation Tolerance.

This book presents design techniques, analysis and implementation of high performance and power efficient, variation tolerant on-chip interconnects.  Given the design paradigm shift to multi-core, interconnect-centric designs and the increase in sources of variability and their impact in sub-100nm technologies, this book will be an invaluable reference for anyone concerned with the design of next generation, high-performance electronics systems. Provides comprehensive, circuit-level explanation of high-performance, energy-efficient, variation-tolerant on-chip interconnect; Describes design techniques to mitigate problems caused by variation; Includes techniques for design and implementation of self-timed on-chip interconnect, delay variation insensitive communication protocols, high speed signaling techniques and circuits, bit-width independent completion detection and process, voltage and temperature variation tolerance.                          

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