Planar Double-Gate Transistor [electronic resource] : From Technology to Circuit / edited by Amara Amara, Olivier Rozeau.Material type: TextLanguage: English Publisher: Dordrecht : Springer Netherlands, 2009Description: VIII, 211 p. online resourceContent type: text Media type: computer Carrier type: online resourceISBN: 9781402093418Subject(s): Engineering | Particles (Nuclear physics) | Systems engineering | Optical materials | Engineering | Circuits and Systems | Solid State Physics and Spectroscopy | Optical and Electronic MaterialsAdditional physical formats: Printed edition:: No titleDDC classification: 621.3815 LOC classification: TK7888.4Online resources: Click here to access online
Multiple Gate Technologies -- Compact Modeling of Independent Double-Gate MOSFET: A Physical Approach -- Compact Modeling of Double Gate MOSFET for IC Design -- Low Frequency Noise in Double-Gate SOI CMOS Devices -- Analog Circuit Design -- Logic Circuit Design with DGMOS Devices -- SRAM Circuit Design.
This book on Double-Gates devices and circuit is unique and aims to reinforce the synergy between the research activities on CMOS sub-32nm devices and the design of elementary cells. The goal is to point out how we can take advantage of new transistor structures to come up with new basic cells and concepts that exploit the electrical features of these new devices and the breakthrough they bring. Planar Double-Gate Transistor will mainly focus on SOI CMOS transistors, fully depleted with double independent planar Gates (Independent Planar Double Gates Transistors: IPDGT), a potential candidate for the sub-32 nm technological nodes as planned by the current ITRS Roadmap. The book topics are mainly focusing on: Detailed description of specific processes that allow the optimization of the CMOS IPDGT device CMOS IPDGT modeling, both compact and physical models are presented Device characterization Design of innovating cells (SRAM cells, basic digital & analog functions) with the objectives to improve the level of integration and the robustness to variability as well as the power consumption optimization, using the degree of freedom introduced by the independent gates.