Retargetable Processor System Integration into Multi-Processor System-on-Chip Platforms [electronic resource] / by Andreas Wieferink, Heinrich Meyr, Rainer Leupers.

By: Wieferink, Andreas [author.]Contributor(s): Meyr, Heinrich [author.] | Leupers, Rainer [author.] | SpringerLink (Online service)Material type: TextTextLanguage: English Publisher: Dordrecht : Springer Netherlands, 2008Description: XIV, 162 p. online resourceContent type: text Media type: computer Carrier type: online resourceISBN: 9781402086526Subject(s): Engineering | Software engineering | Systems engineering | Engineering | Circuits and Systems | Special Purpose and Application-Based SystemsAdditional physical formats: Printed edition:: No titleDDC classification: 621.3815 LOC classification: TK7888.4Online resources: Click here to access online
Contents:
SOC Design Methodologies -- Communication Modeling -- Processor Modeling -- Processor System Integration -- Successive Top-Down Refinement Flow -- Automatic Retargetability -- Debugging and Profiling -- Case Study -- Summary.
In: Springer eBooksSummary: The ever increasing complexity of modern electronic devices together with the continually shrinking time-to-market and product lifetimes pose enormous chip design challenges to meet flexibility, performance and energy efficiency constraints. As a consequence, the current trend is towards programmable platforms (Multi-Processor System-on-Chip Platforms, MP-SoC), which are tailored to the respective target application. In the usual case, a new platform is designed by selecting and assembling standard platform elements. However, best results can only be achieved if the processor cores and the communication modules themselves are also optimized for the target application. Effective exploration is only possible if accurate module simulators are generated automatically based on abstract specifications. As a matter of fact, CoWare’s BusCompiler allows generating accurate simulators for communication modules, and modeling languages such as LISA enable the same for processor cores. In Retargetable Processor System Integration into Multi-Processor System-on-Chip Platforms, such originally independent approaches are combined in order to enable the development of highly optimized programmable platforms. The first chapters of this book summarize the state of the art in all three involved fields separately: general system level design, communication modeling, and processor modeling. The main chapters then present a methodology and the associated tooling for enabling design space exploration as well as a successive refinement flow for the design of optimized MP-SoCs with a high degree of automation.
Tags from this library: No tags from this library for this title. Log in to add tags.
    Average rating: 0.0 (0 votes)
No physical items for this record

SOC Design Methodologies -- Communication Modeling -- Processor Modeling -- Processor System Integration -- Successive Top-Down Refinement Flow -- Automatic Retargetability -- Debugging and Profiling -- Case Study -- Summary.

The ever increasing complexity of modern electronic devices together with the continually shrinking time-to-market and product lifetimes pose enormous chip design challenges to meet flexibility, performance and energy efficiency constraints. As a consequence, the current trend is towards programmable platforms (Multi-Processor System-on-Chip Platforms, MP-SoC), which are tailored to the respective target application. In the usual case, a new platform is designed by selecting and assembling standard platform elements. However, best results can only be achieved if the processor cores and the communication modules themselves are also optimized for the target application. Effective exploration is only possible if accurate module simulators are generated automatically based on abstract specifications. As a matter of fact, CoWare’s BusCompiler allows generating accurate simulators for communication modules, and modeling languages such as LISA enable the same for processor cores. In Retargetable Processor System Integration into Multi-Processor System-on-Chip Platforms, such originally independent approaches are combined in order to enable the development of highly optimized programmable platforms. The first chapters of this book summarize the state of the art in all three involved fields separately: general system level design, communication modeling, and processor modeling. The main chapters then present a methodology and the associated tooling for enabling design space exploration as well as a successive refinement flow for the design of optimized MP-SoCs with a high degree of automation.

There are no comments on this title.

to post a comment.

Implemented and Maintained by Biju Patnaik Central Library.
For any Suggestions/Query Contact to library or Email: library@nitrkl.ac.in OR bpcl-cir@nitrkl.ac.in. Ph:91+6612462103
Website/OPAC best viewed in Mozilla Browser in 1366X768 Resolution.

Powered by Koha