Embedded Systems Specification and Design Languages [electronic resource] : Selected contributions from FDL’07 / edited by Eugenio Villar.Material type: TextLanguage: English Series: Lecture Notes in Electrical Engineering: 10Publisher: Dordrecht : Springer Netherlands, 2008Description: online resourceContent type: text Media type: computer Carrier type: online resourceISBN: 9781402082979Subject(s): Engineering | Computer hardware | Software engineering | Systems engineering | Engineering | Circuits and Systems | Computer Hardware | Special Purpose and Application-Based Systems | Software Engineering/Programming and Operating SystemsAdditional physical formats: Printed edition:: No titleDDC classification: 621.3815 LOC classification: TK7888.4Online resources: Click here to access online
C/C++ Based System Design -- How Different Are Esterel and SystemC -- Timed Asynchronous Circuits Modeling and Validation Using SystemC -- On Construction of Cycle Approximate Bus TLMs -- Combinatorial Dependencies in Transaction Level Models -- An Integrated SystemC Debugging Environment -- Measuring the Quality of a SystemC Testbench by Using Code Coverage Techniques -- SystemC-Based Simulation of the MICAS Architecture -- Analog, Mixed-Signal, and Heterogeneous System Design -- Heterogeneous Specification with HetSC and SystemC-AMS: Widening the Support of MoCs in SystemC -- An Extension to VHDL-AMS for AMS Systems with Partial Differential Equations -- Mixed-Level Modeling Using Configurable MOS Transistor Models -- UML-Based System Specification and Design -- Modeling AADL Data Communications with UML MARTE -- Software Real-Time Resource Modeling -- Model Transformations from a Data Parallel Formalism Towards Synchronous Languages -- UML and SystemC – A Comparison and Mapping Rules for Automatic Code Generation -- An Enhanced SystemC UML Profile for Modeling at Transaction-Level -- SC2 StateCharts to SystemC: Automatic Executable Models Generation -- Formalisms for Property-Driven Design -- Asynchronous On-Line Monitoring of Logical and Temporal Assertions -- Transactor-Based Formal Verification of Real-Time Embedded Systems -- A Case-Study in Property-Based Synthesis: Generating a Cache Controller from a Property-Set.
FDL is the most important European and, probably, worldwide forum to present research results, to exchange experiences, and to learn about new trends in the application of specification and design languages and the associated design and modeling methods and tools for complex, heterogeneous HW/SW embedded systems. FDL’07 was the tenth of a series of successful events held all around Europe. FDL’07 was held in Barcelona, the capital city of Catalonia, Spain. The high number of submissions to the conference this year allowed the Program Committee to prepare a high quality conference program. Embedded Systems Specification and Design Languages includes a selection of the most relevant contributions based on the review made by the program committee members and the quality of the contents of the presentation at the conference. In many cases, the authors have improved the original content with additional technical information. The papers cover the most important aspects in system modeling and specification, an essential area in Embedded Systems design. The objective of Embedded Systems Specification and Design Languages is to serve as a reference text for researchers and designers interested in the extension and improvement of the application of design and verification languages in the area of Embedded Systems.