Full-Chip Nanometer Routing Techniques [electronic resource] / by Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen.

By: Ho, Tsung-Yi [author.]Contributor(s): Chang, Yao-Wen [author.] | Chen, Sao-Jie [author.] | SpringerLink (Online service)Material type: TextTextLanguage: English Series: Analog Circuits And Signal Processing Series: Publisher: Dordrecht : Springer Netherlands, 2007Description: XVIII, 102 p. online resourceContent type: text Media type: computer Carrier type: online resourceISBN: 9781402061950Subject(s): Engineering | Computer aided design | Systems engineering | Nanotechnology | Engineering | Circuits and Systems | Computer-Aided Engineering (CAD, CAE) and Design | NanotechnologyAdditional physical formats: Printed edition:: No titleDDC classification: 621.3815 LOC classification: TK7888.4Online resources: Click here to access online
Contents:
Routing Challenges for Nanometer Technology -- Multilevel Full-Chip Routing Considering Crosstalk And Performance -- Multilevel Full-Chip Routing Considering Antenna Effect Avoidance -- Multilevel Full-Chip Routing For The X-Based Architecture -- Concluding Remarks And Future Work.
In: Springer eBooksSummary: As Moore's Law continues unencumbered into the nanometer era, chips are reaching 1000 M gates in size, process geometries have shrunk to 90 nm and below, and engineers have to face compounded design complexity with every new design. These nanometer-scale designs require a new generation of physics-aware and manufacturing-aware routing. At 90 nm and below, there are so many signal-integrity issues that design teams cannot manually correct them all. At 90 nm, wires account for nearly 75% of the total delay in a circuit. Even more insidious, however, is that among nearly 40% of these nets, more than 50% of their total net capacitance are attributed to the cross-coupling capacitance between neighboring signals. At this point a new design and optimization paradigm based on real wires is required. Nanometer routers must prevent and correct these effects on-the-fly in order to reach timing closure. From a manufacturability standpoint, nanometer routers must explicitly deal with the ever increasing design complexity, and be capable of adapting to the constraint requirements of timing, signal integrity, process antenna effect, and new interconnect architecture such as X-architecture. In the nanometer era, we must look into new-generation routing technologies that combine high performance and capacity with the integration of congestion, timing, SI prevention, and DFM algorithms as the best means of getting to design closure quickly. In this book, we present a novel multilevel full-chip router, namely mSIGMA for SIGnal-integrity and MAnufacturability optimization. And these routing technologies will ensure faster time-to-market and time-to-profitability.
Tags from this library: No tags from this library for this title. Log in to add tags.
    Average rating: 0.0 (0 votes)
No physical items for this record

Routing Challenges for Nanometer Technology -- Multilevel Full-Chip Routing Considering Crosstalk And Performance -- Multilevel Full-Chip Routing Considering Antenna Effect Avoidance -- Multilevel Full-Chip Routing For The X-Based Architecture -- Concluding Remarks And Future Work.

As Moore's Law continues unencumbered into the nanometer era, chips are reaching 1000 M gates in size, process geometries have shrunk to 90 nm and below, and engineers have to face compounded design complexity with every new design. These nanometer-scale designs require a new generation of physics-aware and manufacturing-aware routing. At 90 nm and below, there are so many signal-integrity issues that design teams cannot manually correct them all. At 90 nm, wires account for nearly 75% of the total delay in a circuit. Even more insidious, however, is that among nearly 40% of these nets, more than 50% of their total net capacitance are attributed to the cross-coupling capacitance between neighboring signals. At this point a new design and optimization paradigm based on real wires is required. Nanometer routers must prevent and correct these effects on-the-fly in order to reach timing closure. From a manufacturability standpoint, nanometer routers must explicitly deal with the ever increasing design complexity, and be capable of adapting to the constraint requirements of timing, signal integrity, process antenna effect, and new interconnect architecture such as X-architecture. In the nanometer era, we must look into new-generation routing technologies that combine high performance and capacity with the integration of congestion, timing, SI prevention, and DFM algorithms as the best means of getting to design closure quickly. In this book, we present a novel multilevel full-chip router, namely mSIGMA for SIGnal-integrity and MAnufacturability optimization. And these routing technologies will ensure faster time-to-market and time-to-profitability.

There are no comments on this title.

to post a comment.

Implemented and Maintained by Biju Patnaik Central Library.
For any Suggestions/Query Contact to library or Email: library@nitrkl.ac.in OR bpcl-cir@nitrkl.ac.in. Ph:91+6612462103
Website/OPAC best viewed in Mozilla Browser in 1366X768 Resolution.

Powered by Koha