Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies [electronic resource] / by Stephan Henzler.Material type: TextLanguage: English Series: Advanced Microelectronics: 25Publisher: Dordrecht : Springer Netherlands, 2007Description: XVI, 186 p. online resourceContent type: text Media type: computer Carrier type: online resourceISBN: 9781402050817Subject(s): Engineering | Particles (Nuclear physics) | Electronics | Systems engineering | Nanotechnology | Engineering | Circuits and Systems | Power Engineering | Electronic and Computer Engineering | Solid State Physics and Spectroscopy | Electronics and Microelectronics, Instrumentation | NanotechnologyAdditional physical formats: Printed edition:: No titleDDC classification: 621.3815 LOC classification: TK7888.4Online resources: Click here to access online
TO LOW-POWER DIGITAL INTEGRATED CIRCUIT DESIGN -- LOGIC WITH MULTIPLE SUPPLY VOLTAGES -- LOGIC WITH MULTIPLE THRESHOLD VOLTAGES -- FORCING OF TRANSISTOR STACKS -- POWER GATING -- CONCLUSION.
In the deep sub-micron regime, the power consumption has become one of the most important issues for competitive design of digital circuits. Due to dramatically increasing leakage currents, the power consumption does not take advantage of technology scaling as before. State-of-art power reduction techniques like the use of multiple supply and threshold voltages, transistor stack forcing and power gating are discussed with respect to implementation and power saving capability. Focus is given especially on technology dependencies, process variations and technology scaling. Design and implementation issues are discussed with respect to the trade-off between power reduction, performance degradation, and system level constraints. A complete top-down design flow is demonstrated for power gating techniques introducing new design methodologies for the switch sizing task and circuit blocks for data-retention and block activation. The leakage reduction ratio and the minimum power-down time are introduced as figures of merit to describe the power gating technique on system level and give a relation to physical circuit parameters. Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies mainly deals with circuit design but also addresses the interface between circuit and system level design on the one side and between circuit and physical design on the other side.