SystemVerilog for Design (Record no. 654)

000 -LEADER
fixed length control field 04953nam a22005415i 4500
001 - CONTROL NUMBER
control field 978-0-387-36495-7
003 - CONTROL NUMBER IDENTIFIER
control field DE-He213
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20141014113430.0
007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION
fixed length control field cr nn 008mamaa
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 100301s2006 xxu| s |||| 0|eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9780387364957
-- 978-0-387-36495-7
024 7# - OTHER STANDARD IDENTIFIER
Standard number or code 10.1007/0-387-36495-1
Source of number or code doi
041 ## - LANGUAGE CODE
Language code of text/sound track or separate title eng
050 #4 - LIBRARY OF CONGRESS CALL NUMBER
Classification number TK7888.4
072 #7 - SUBJECT CATEGORY CODE
Subject category code TJFC
Source bicssc
072 #7 - SUBJECT CATEGORY CODE
Subject category code TEC008010
Source bisacsh
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621.3815
Edition number 23
100 1# - MAIN ENTRY--PERSONAL NAME
Personal name Sutherland, Stuart.
Relator term author.
245 10 - TITLE STATEMENT
Title SystemVerilog for Design
Medium [electronic resource] :
Remainder of title A Guide to Using SystemVerilog for Hardware Design and Modeling /
Statement of responsibility, etc by Stuart Sutherland, Simon Davidmann, Peter Flake.
250 ## - EDITION STATEMENT
Edition statement Second Edition.
260 #1 - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT)
Place of publication, distribution, etc Boston, MA :
Name of publisher, distributor, etc Springer US,
Date of publication, distribution, etc 2006.
264 #1 -
-- Boston, MA :
-- Springer US,
-- 2006.
300 ## - PHYSICAL DESCRIPTION
Extent XXX, 418 p.
Other physical details online resource.
336 ## -
-- text
-- txt
-- rdacontent
337 ## -
-- computer
-- c
-- rdamedia
338 ## -
-- online resource
-- cr
-- rdacarrier
347 ## -
-- text file
-- PDF
-- rda
505 0# - FORMATTED CONTENTS NOTE
Formatted contents note to SystemVerilog -- SystemVerilog Declaration Spaces -- SystemVerilog Literal Values and Built-in Data Types -- SystemVerilog User-Defined and Enumerated Types -- SystemVerilog Arrays, Structures and Unions -- SystemVerilog Procedural Blocks, Tasks and Functions -- SystemVerilog Procedural Statements -- Modeling Finite State Machines with SystemVerilog -- SystemVerilog Design Hierarchy -- SystemVerilog Interfaces -- A Complete Design Modeled with SystemVerilog -- Behavioral and Transaction Level Modeling.
520 ## - SUMMARY, ETC.
Summary, etc SystemVerilog is a rich set of extensions to the Verilog Hardware Description Language (Verilog HDL). SystemVerilog for Design describes the correct usage of these extensions for modeling digital designs. These important extensions enable the representation of complex digital logic in concise, accurate, and reusable hardware models. All key SystemVerilog design features are presented, such as declaration spaces, two-state data types, enumerated types, user-defined types, structures, unions, interfaces, and RTL coding extensions. Emphasis is placed on the proper usage of these enhancements for simulation and synthesis. Design engineers, engineering managers and engineering students working with all sizes and types of digital designs, whether FPGA, ASIC or full custom, will find this book to be an invaluable learning tool and reference guide. The second edition of this book reflects the official IEEE 1800-2005 SystemVerilog standard. This IEEE SystemVerilog standard adds new capabilities, clarifications, and changes to the Accellera 3.1 SystemVerilog upon which the first edition of this book was based. Significant updates and revisions in the new edition include: A new chapter showing how to use SystemVerilog packages with single-file and multi-file compilers. - New code examples illustrating correct usage of the IEEE version of SystemVerilog. - Updated coding guidelines reflecting the capabilities of current simulator and synthesis Electronic Design Automation tools such as digital simulators and synthesis compilers. "SystemVerilog makes it easier to produce more efficient and concise descriptions of complex hardware designs. The authors of this book have been involved with the development of the language from the beginning, and who is better to learn from than those involved from day one?" — Greg Spirakis, Vice President of Design Technology Intel Corporation "Sun has been a driving force in SystemVerilog from its inception. SystemVerilog can significantly improve the productivity of designers in the coming years, and this book is a comprehensive reference text for engineers who want to learn about SystemVerilog for their next generation designs." — Sunil Joshi, Vice President of Software Technologies & Compute Resources Sun Microsystems, Inc. "SystemVerilog addresses the need for efficient and powerful modeling essential to support the complexity, size and scale of next generation hardware designs. This book explains how to use SystemVerilog effectively and provides numerous examples to illustrate how each of the language constructs can best be utilized." — Chris Malachowsky, Co-Founder and Vice President of Hardware NVIDIA Corp.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Engineering.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Computer hardware.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Computer aided design.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Systems engineering.
650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Engineering.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Circuits and Systems.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Computer-Aided Engineering (CAD, CAE) and Design.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Computer Hardware.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Electronic and Computer Engineering.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Davidmann, Simon.
Relator term author.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Flake, Peter.
Relator term author.
710 2# - ADDED ENTRY--CORPORATE NAME
Corporate name or jurisdiction name as entry element SpringerLink (Online service)
773 0# - HOST ITEM ENTRY
Title Springer eBooks
776 08 - ADDITIONAL PHYSICAL FORM ENTRY
Display text Printed edition:
International Standard Book Number 9780387333991
856 40 - ELECTRONIC LOCATION AND ACCESS
Uniform Resource Identifier http://dx.doi.org/10.1007/0-387-36495-1
912 ## -
-- ZDB-2-ENG
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type E-Books

No items available.


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