Digital System Test and Testable Design (Record no. 1542)
[ view plain ]
| 000 -LEADER | |
|---|---|
| fixed length control field | 03795nam a22004695i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 978-1-4419-7548-5 |
| 003 - CONTROL NUMBER IDENTIFIER | |
| control field | DE-He213 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20141014113444.0 |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION | |
| fixed length control field | cr nn 008mamaa |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 101210s2011 xxu| s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9781441975485 |
| -- | 978-1-4419-7548-5 |
| 024 7# - OTHER STANDARD IDENTIFIER | |
| Standard number or code | 10.1007/978-1-4419-7548-5 |
| Source of number or code | doi |
| 041 ## - LANGUAGE CODE | |
| Language code of text/sound track or separate title | eng |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER | |
| Classification number | TK7888.4 |
| 072 #7 - SUBJECT CATEGORY CODE | |
| Subject category code | TJFC |
| Source | bicssc |
| 072 #7 - SUBJECT CATEGORY CODE | |
| Subject category code | TEC008010 |
| Source | bisacsh |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.3815 |
| Edition number | 23 |
| 100 1# - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Navabi, Zainalabedin. |
| Relator term | author. |
| 245 10 - TITLE STATEMENT | |
| Title | Digital System Test and Testable Design |
| Medium | [electronic resource] : |
| Remainder of title | Using HDL Models and Architectures / |
| Statement of responsibility, etc | by Zainalabedin Navabi. |
| 260 #1 - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
| Place of publication, distribution, etc | Boston, MA : |
| Name of publisher, distributor, etc | Springer US : |
| -- | Imprint: Springer, |
| Date of publication, distribution, etc | 2011. |
| 264 #1 - | |
| -- | Boston, MA : |
| -- | Springer US : |
| -- | Imprint: Springer, |
| -- | 2011. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | XVII, 435p. 100 illus. |
| Other physical details | online resource. |
| 336 ## - | |
| -- | text |
| -- | txt |
| -- | rdacontent |
| 337 ## - | |
| -- | computer |
| -- | c |
| -- | rdamedia |
| 338 ## - | |
| -- | online resource |
| -- | cr |
| -- | rdacarrier |
| 347 ## - | |
| -- | text file |
| -- | |
| -- | rda |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | Digital System Test and Testable Design: Using HDL Models and Architectures by: Zainalabedin Navabi This book is about digital system test and testable design. The concepts of testing and testability are treated together with digital design practices and methodologies. The book uses Verilog models and testbenches for implementing and explaining fault simulation and test generation algorithms. Extensive use of Verilog and Verilog PLI for test applications is what distinguishes this book from other test and testability books. Verilog eliminates ambiguities in test algorithms and BIST and DFT hardware architectures, and it clearly describes the architecture of the testability hardware and its test sessions. Describing many of the on-chip decompression algorithms in Verilog helps to evaluate these algorithms in terms of hardware overhead and timing, and thus feasibility of using them for System-on-Chip designs. Extensive use of testbenches and testbench development techniques is another unique feature of this book. Using PLI in developing testbenches and virtual testers provides a powerful programming tool, interfaced with hardware described in Verilog. This mixed hardware / software environment facilitates description of complex test programs and test strategies. •Combines design and test •Describes test methods in Verilog and PLI, which makes the methods more understandable and the gates possible to simulate •Simulation of gate models allows fault simulation and test generation, while Verilog testbenches inject faults, evaluate fault coverage and apply new test patterns •Describes DFT, compression, decompression, and BIST techniques in Verilog, which makes the hardware of the architectures easier to understand and allows simulation and evaluation of the testability methods •Virtual testers (Verilog testbenches) play the role of ATEs for driving scan tests and examining the circuit under test •Verilog descriptions of scan designs and BIST architectures are available that can be used in actual designs •PLI test utilities developed in-text are available for download •Introductory Video for Verilog basics, software developed in-text, and PLI basics available for download •Powerpoint slides available for each chapter |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Science (General). |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Mathematics. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Systems engineering. |
| 650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Popular Science. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Circuits and Systems. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Mathematics, general. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Philosophy. |
| 710 2# - ADDED ENTRY--CORPORATE NAME | |
| Corporate name or jurisdiction name as entry element | SpringerLink (Online service) |
| 773 0# - HOST ITEM ENTRY | |
| Title | Springer eBooks |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY | |
| Display text | Printed edition: |
| International Standard Book Number | 9781441975478 |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | http://dx.doi.org/10.1007/978-1-4419-7548-5 |
| 912 ## - | |
| -- | ZDB-2-ENG |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | E-Books |
No items available.
