Yuan, Jun.

Constraint-Based Verification [electronic resource] / by Jun Yuan, Carl Pixley, Adnan Aziz. - Boston, MA : Springer US, 2006. - XII, 253 p. online resource.

Constrained Random Simulation -- High Level Verification Languages -- Assertion Languages and Constraints -- Preliminaries -- Constrained Vector Generation -- Constraint Simplification -- More Optimizations -- Constraint Synthesis -- Constraint Diagnosis -- Word-Level Constraint Solving.

Constraint-Based Verifcation covers the emerging field in functional verification of electronic designs thats is now commonly referred to by this name. Topics are developed in the context of a wide range of dynamic and static verification approaches including stimulation, emulation and formal methods. The goal is to show how constraints, or assertions, can be used toward automating the generation of testbenches, resulting in a seamless verifcation flow. Topics such as verification coverage, and connection with assertion-based verification are also covered. Constraint-Based Verification is written for verification engineers, as well as researchers - it explains both methodological and technical issues. Particular stress is given to the latest advances in functional verification.


10.1007/0-387-30784-2 doi

Computer aided design.
Systems engineering.
Circuits and Systems.
Computer-Aided Engineering (CAD, CAE) and Design.
Electronic and Computer Engineering.



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