Normal view MARC view ISBD view

Fault-Tolerance Techniques for SRAM-based FPGAs [electronic resource] / by Fernanda Lima Kastensmidt, Luigi Carro, Ricardo Reis.

By: Kastensmidt, Fernanda Lima [author.].
Contributor(s): Carro, Luigi [author.] | Reis, Ricardo [author.] | SpringerLink (Online service).
Material type: materialTypeLabelBookPublisher: Boston, MA : Springer US, 2006Description: XVI, 184 p. online resource.Content type: text Media type: computer Carrier type: online resourceISBN: 9780387310695.Subject(s): Engineering | Logic design | Operating systems (Computers) | Engineering design | Electronics | Optical materials | Engineering | Electronic and Computer Engineering | Optical and Electronic Materials | Electronics and Microelectronics, Instrumentation | Engineering Design | Performance and Reliability | Logic DesignDDC classification: 621.3 Online resources: Click here to access online
Contents:
Radiation Effects in Integrated Circuits -- Single Event Upset (SEU) Mitigation Techniques -- Architectural SEU Mitigation Techniques -- High-Level SEU Mitigation Techniques -- Triple Modular Redundancy (TMR) Robustness -- Designing and Testing a TMR Micro-Controller -- Reducing TMR Overheads: Part I -- Reducing TMR Overheads: Part II -- Final Remarks.
In: Springer eBooksSummary: Fault-tolerance in integrated circuits is not an exclusive concern regarding space designers or highly-reliable application engineers. Rather, designers of next generation products must cope with reduced margin noises due to technological advances. The continuous evolution of the fabrication technology process of semiconductor components, in terms of transistor geometry shrinking, power supply, speed, and logic density, has significantly reduced the reliability of very deep submicron integrated circuits, in face of the various internal and external sources of noise. The very popular Field Programmable Gate Arrays, customizable by SRAM cells, are a consequence of the integrated circuit evolution with millions of memory cells to implement the logic, embedded memories, routing, and more recently with embedded microprocessors cores. These re-programmable systems-on-chip platforms must be fault-tolerant to cope with present days requirements. This book discusses fault-tolerance techniques for SRAM-based Field Programmable Gate Arrays (FPGAs). It starts by showing the model of the problem and the upset effects in the programmable architecture. In the sequence, it shows the main fault tolerance techniques used nowadays to protect integrated circuits against errors. A large set of methods for designing fault tolerance systems in SRAM-based FPGAs is described. Some presented techniques are based on developing a new fault-tolerant architecture with new robustness FPGA elements. Other techniques are based on protecting the high-level hardware description before the synthesis in the FPGA. The reader has the flexibility of choosing the most suitable fault-tolerance technique for its project and to compare a set of fault tolerant techniques for programmable logic applications.
Tags from this library: No tags from this library for this title. Log in to add tags.
    average rating: 0.0 (0 votes)
No physical items for this record

Radiation Effects in Integrated Circuits -- Single Event Upset (SEU) Mitigation Techniques -- Architectural SEU Mitigation Techniques -- High-Level SEU Mitigation Techniques -- Triple Modular Redundancy (TMR) Robustness -- Designing and Testing a TMR Micro-Controller -- Reducing TMR Overheads: Part I -- Reducing TMR Overheads: Part II -- Final Remarks.

Fault-tolerance in integrated circuits is not an exclusive concern regarding space designers or highly-reliable application engineers. Rather, designers of next generation products must cope with reduced margin noises due to technological advances. The continuous evolution of the fabrication technology process of semiconductor components, in terms of transistor geometry shrinking, power supply, speed, and logic density, has significantly reduced the reliability of very deep submicron integrated circuits, in face of the various internal and external sources of noise. The very popular Field Programmable Gate Arrays, customizable by SRAM cells, are a consequence of the integrated circuit evolution with millions of memory cells to implement the logic, embedded memories, routing, and more recently with embedded microprocessors cores. These re-programmable systems-on-chip platforms must be fault-tolerant to cope with present days requirements. This book discusses fault-tolerance techniques for SRAM-based Field Programmable Gate Arrays (FPGAs). It starts by showing the model of the problem and the upset effects in the programmable architecture. In the sequence, it shows the main fault tolerance techniques used nowadays to protect integrated circuits against errors. A large set of methods for designing fault tolerance systems in SRAM-based FPGAs is described. Some presented techniques are based on developing a new fault-tolerant architecture with new robustness FPGA elements. Other techniques are based on protecting the high-level hardware description before the synthesis in the FPGA. The reader has the flexibility of choosing the most suitable fault-tolerance technique for its project and to compare a set of fault tolerant techniques for programmable logic applications.

There are no comments for this item.

Log in to your account to post a comment.


Implemented and Maintained by Biju Patnaik Central Library.
For any Suggestions/Query Contact to library or Email: library@nitrkl.ac.in OR bpcl-cir@nitrkl.ac.in. Ph:91+6612462103
Website/OPAC best viewed in Mozilla Browser in 1366X768 Resolution.

Powered by Koha