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Design of Very High-Frequency Multirate Switched-Capacitor Circuits [electronic resource] : Extending the Boundaries of CMOS Analog Front-End Filtering / by Seng-Pan U, Rui Paulo Martins, José Epifânio Franca.

By: U, Seng-Pan [author.].
Contributor(s): Martins, Rui Paulo [author.] | Franca, José Epifânio [author.] | SpringerLink (Online service).
Material type: materialTypeLabelBookSeries: The International Series in Engineering and Computer Science, Analog Circuits and Signal Processing: 867Publisher: Boston, MA : Springer US, 2006Description: XXXII, 227 p. online resource.Content type: text Media type: computer Carrier type: online resourceISBN: 9780387261225.Subject(s): Engineering | Engineering design | Electronics | Systems engineering | Engineering | Circuits and Systems | Electronic and Computer Engineering | Engineering Design | Electronics and Microelectronics, InstrumentationDDC classification: 621.3815 Online resources: Click here to access online
Contents:
Improved Multirate Polyphase-Based Interpolation Structures -- Practical Multirate SC Circuit Design Considerations -- Gain- and Offset- Compensation for Multirate SC Circuits -- Design of a 108 MHz Multistage SC Video Interpolating Filter -- Design of a 320 MHz Frequency-Translated SC Bandpass Interpolating Filter -- Experimental Results -- Conclusions.
In: Springer eBooksSummary: Design of Very High-Frequency Multirate Switched-Capacitor Circuits presents the theory and the corresponding CMOS implementation of the novel multirate sampled-data analog interpolation technique which has its great potential on very high-frequency analog frond-end filtering due to its inherent dual advantage of reducing the speed of data-converters and DSP core together with the specification relaxation of the post continuous-time filtering. This technique completely eliminates the traditional phenomenon of sampled-and-hold frequency-shaping at the lower input sampling rate. Also, in order to tackle physical IC imperfections at very high frequency, the state-of-the-art circuit design and layout techniques for high-speed Switched-Capacitor (SC) circuits are comprehensively discussed: -Optimum circuit architecture tradeoff analysis -Simple speed and power trade-off analysis of active elements -High-order filtering response accuracy with respect to capacitor-ratio mismatches -Time-interleaved effect with respect to gain and offset mismatch -Time-interleaved effect with respect to timing-skew and random jitter with non-uniformly holding -Stage noise analysis and allocation scheme -Substrate and supply noise reduction -Gain-and offset-compensation techniques -High-bandwidth low-power amplifier design and layout -Very low timing-skew multiphase generation Two tailor-made optimum design examples in CMOS are presented. The first one achieves a 3-stage 8-fold SC interpolating filter with 5.5MHz bandwidth and 108MHz output sampling rate for a NTSC/PAL CCIR 601 digital video at 3 V. Another is a 15-tap 57MHz SC FIR bandpass interpolating filter with 4-fold sampling rate increase to 320MHz and the first-time embedded frequency band up-translation for DDFS system at 2.5V. The corresponding chip prototype achieves so far the highest operating frequency, highest filter order and highest center frequency with highest dynamic range under the lowest supply voltage when compared to the previously reported high-frequency SC filters in CMOS.
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Improved Multirate Polyphase-Based Interpolation Structures -- Practical Multirate SC Circuit Design Considerations -- Gain- and Offset- Compensation for Multirate SC Circuits -- Design of a 108 MHz Multistage SC Video Interpolating Filter -- Design of a 320 MHz Frequency-Translated SC Bandpass Interpolating Filter -- Experimental Results -- Conclusions.

Design of Very High-Frequency Multirate Switched-Capacitor Circuits presents the theory and the corresponding CMOS implementation of the novel multirate sampled-data analog interpolation technique which has its great potential on very high-frequency analog frond-end filtering due to its inherent dual advantage of reducing the speed of data-converters and DSP core together with the specification relaxation of the post continuous-time filtering. This technique completely eliminates the traditional phenomenon of sampled-and-hold frequency-shaping at the lower input sampling rate. Also, in order to tackle physical IC imperfections at very high frequency, the state-of-the-art circuit design and layout techniques for high-speed Switched-Capacitor (SC) circuits are comprehensively discussed: -Optimum circuit architecture tradeoff analysis -Simple speed and power trade-off analysis of active elements -High-order filtering response accuracy with respect to capacitor-ratio mismatches -Time-interleaved effect with respect to gain and offset mismatch -Time-interleaved effect with respect to timing-skew and random jitter with non-uniformly holding -Stage noise analysis and allocation scheme -Substrate and supply noise reduction -Gain-and offset-compensation techniques -High-bandwidth low-power amplifier design and layout -Very low timing-skew multiphase generation Two tailor-made optimum design examples in CMOS are presented. The first one achieves a 3-stage 8-fold SC interpolating filter with 5.5MHz bandwidth and 108MHz output sampling rate for a NTSC/PAL CCIR 601 digital video at 3 V. Another is a 15-tap 57MHz SC FIR bandpass interpolating filter with 4-fold sampling rate increase to 320MHz and the first-time embedded frequency band up-translation for DDFS system at 2.5V. The corresponding chip prototype achieves so far the highest operating frequency, highest filter order and highest center frequency with highest dynamic range under the lowest supply voltage when compared to the previously reported high-frequency SC filters in CMOS.

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