60-GHz CMOS Phase-Locked Loops [electronic resource] / by Hammad M. Cheema, Reza Mahmoudi, Arthur H. M. Roermund.

By: Cheema, Hammad M [author.]Contributor(s): Mahmoudi, Reza [author.] | Roermund, Arthur H. M [author.] | SpringerLink (Online service)Material type: TextTextLanguage: English Publisher: Dordrecht : Springer Netherlands : Imprint: Springer, 2010Description: IV, 218p. 155 illus., 8 illus. in color. online resourceContent type: text Media type: computer Carrier type: online resourceISBN: 9789048192809Subject(s): Engineering | Microwaves | Systems engineering | Engineering | Circuits and Systems | Microwaves, RF and Optical Engineering | Solid State PhysicsAdditional physical formats: Printed edition:: No titleDDC classification: 621.3815 LOC classification: TK7888.4Online resources: Click here to access online
Contents:
Synthesizer System Architecture -- Layout and Measurements at mm-Wave Frequencies -- Design of High Frequency Components -- Design of Low Frequency Components -- Synthesizer Integration -- Conclusions.
In: Springer eBooksSummary: The promising high data rate wireless applications at millimeter wave frequencies in general and 60 GHz in particular have gained much attention in recent years. However, challenges related to circuit, layout and measurements during mm-wave CMOS IC design have to be overcome before they can become viable for mass market. 60-GHz CMOS Phase-Locked Loops focusing on phase-locked loops for 60 GHz wireless transceivers elaborates these challenges and proposes solutions for them. The system level design to circuit level implementation of the complete PLL, along with separate implementations of individual components such as voltage controlled oscillators, injection locked frequency dividers and their combinations, are included. Furthermore, to satisfy a number of transceiver topologies simultaneously, flexibility is introduced in the PLL architecture by using new dual-mode ILFDs and switchable VCOs, while reusing the low frequency components at the same time.
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Synthesizer System Architecture -- Layout and Measurements at mm-Wave Frequencies -- Design of High Frequency Components -- Design of Low Frequency Components -- Synthesizer Integration -- Conclusions.

The promising high data rate wireless applications at millimeter wave frequencies in general and 60 GHz in particular have gained much attention in recent years. However, challenges related to circuit, layout and measurements during mm-wave CMOS IC design have to be overcome before they can become viable for mass market. 60-GHz CMOS Phase-Locked Loops focusing on phase-locked loops for 60 GHz wireless transceivers elaborates these challenges and proposes solutions for them. The system level design to circuit level implementation of the complete PLL, along with separate implementations of individual components such as voltage controlled oscillators, injection locked frequency dividers and their combinations, are included. Furthermore, to satisfy a number of transceiver topologies simultaneously, flexibility is introduced in the PLL architecture by using new dual-mode ILFDs and switchable VCOs, while reusing the low frequency components at the same time.

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