Normal view MARC view ISBD view

Designing Reliable and Efficient Networks on Chips [electronic resource] / by Srinivasan Murali.

By: Murali, Srinivasan [author.].
Contributor(s): SpringerLink (Online service).
Material type: materialTypeLabelBookSeries: Lecture Notes in Electrical Engineering: 34Publisher: Dordrecht : Springer Netherlands, 2009Description: X, 198 p. online resource.Content type: text Media type: computer Carrier type: online resourceISBN: 9781402097577.Subject(s): Engineering | Computer science | Systems engineering | Engineering | Circuits and Systems | Processor ArchitecturesDDC classification: 621.3815 Online resources: Click here to access online
Contents:
NoC Design Methods -- Designing Crossbar Based Systems -- Netchip Tool Flow for NoC Design -- Designing Standard Topologies -- Designing Custom Topologies -- Supporting Multiple Applications -- Supporting Dynamic Application Patterns -- NoC Reliability Mechanisms -- Timing-Error Tolerant NoC Design -- Analysis of NoC Error Recovery Schemes -- Fault-Tolerant Route Generation -- NoC Support for Reliable On-Chip Memories -- Conclusions and Future Directions.
In: Springer eBooksSummary: Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another important design challenge for NoCs will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. The purpose of Designing Reliable and Efficient Networks on Chips is to provide state-of-the-art methods to solve some of the most important and time-intensive problems encountered during NoC design.
Tags from this library: No tags from this library for this title. Log in to add tags.
    average rating: 0.0 (0 votes)
No physical items for this record

NoC Design Methods -- Designing Crossbar Based Systems -- Netchip Tool Flow for NoC Design -- Designing Standard Topologies -- Designing Custom Topologies -- Supporting Multiple Applications -- Supporting Dynamic Application Patterns -- NoC Reliability Mechanisms -- Timing-Error Tolerant NoC Design -- Analysis of NoC Error Recovery Schemes -- Fault-Tolerant Route Generation -- NoC Support for Reliable On-Chip Memories -- Conclusions and Future Directions.

Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another important design challenge for NoCs will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. The purpose of Designing Reliable and Efficient Networks on Chips is to provide state-of-the-art methods to solve some of the most important and time-intensive problems encountered during NoC design.

There are no comments for this item.

Log in to your account to post a comment.


Implemented and Maintained by Biju Patnaik Central Library.
For any Suggestions/Query Contact to library or Email: library@nitrkl.ac.in OR bpcl-cir@nitrkl.ac.in. Ph:91+6612462103
Website/OPAC best viewed in Mozilla Browser in 1366X768 Resolution.

Powered by Koha