Co-design for System Acceleration [electronic resource] : A Quantitative Approach / by Nadia Nedjah, Luiza De Macedo Mourelle.

By: Nedjah, Nadia [author.]Contributor(s): Mourelle, Luiza De Macedo [author.] | SpringerLink (Online service)Material type: TextTextLanguage: English Publisher: Dordrecht : Springer Netherlands, 2007Description: XIX, 229 p. online resourceContent type: text Media type: computer Carrier type: online resourceISBN: 9781402055461Subject(s): Engineering | Computer hardware | Memory management (Computer science) | Computer network architectures | Computer science | Systems engineering | Engineering | Circuits and Systems | Computer Hardware | Computer Systems Organization and Communication Networks | Memory Structures | Processor ArchitecturesAdditional physical formats: Printed edition:: No titleDDC classification: 621.3815 LOC classification: TK7888.4Online resources: Click here to access online
Contents:
The Co-design Methodology -- The Co-design System -- VHDL Model of the Co-design System -- Shared Memory Configuration -- Dual-port Memory Configuration -- Cache Memory Configuration -- Advanced Topics and Further Research.
In: Springer eBooksSummary: In Co-Design for System Acceleration, we are concerned with studying the co-design methodology, in general, and how to determine the more suitable interface mechanism in a co-design system, in particular. This will be based on the characteristics of the application and those of the target architecture of the system. We provide guidelines to support the designer's choice of the interface mechanism. The content of Co-Design for System Acceleration is divided into eight chapters. We present co-design as a methodology for the integrated design of systems implemented using both hardware and software components. This includes high-level synthesis and the new technologies available for its implementation. The physical co-design system is then presented. The development route adopted is discussed and the target architecture described. The relation between the execution times and the interface mechanisms is analyzed. In order to investigate the performance of the co-design system for different characteristics of the application and of the architecture, we developed a VHDL model of our co-design system. The timing characteristics of the system are introduced, that is times for parameter passing and bus arbitration for each interface mechanism, together with their handshake completion times. The relation between the coprocessor memory accesses and the interface mechanisms is then studied. Several memory configurations are presented and studied: single-port memory, dual-port memory and cache memory. We also introduce some new trends in co-design and system acceleration.
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The Co-design Methodology -- The Co-design System -- VHDL Model of the Co-design System -- Shared Memory Configuration -- Dual-port Memory Configuration -- Cache Memory Configuration -- Advanced Topics and Further Research.

In Co-Design for System Acceleration, we are concerned with studying the co-design methodology, in general, and how to determine the more suitable interface mechanism in a co-design system, in particular. This will be based on the characteristics of the application and those of the target architecture of the system. We provide guidelines to support the designer's choice of the interface mechanism. The content of Co-Design for System Acceleration is divided into eight chapters. We present co-design as a methodology for the integrated design of systems implemented using both hardware and software components. This includes high-level synthesis and the new technologies available for its implementation. The physical co-design system is then presented. The development route adopted is discussed and the target architecture described. The relation between the execution times and the interface mechanisms is analyzed. In order to investigate the performance of the co-design system for different characteristics of the application and of the architecture, we developed a VHDL model of our co-design system. The timing characteristics of the system are introduced, that is times for parameter passing and bus arbitration for each interface mechanism, together with their handshake completion times. The relation between the coprocessor memory accesses and the interface mechanisms is then studied. Several memory configurations are presented and studied: single-port memory, dual-port memory and cache memory. We also introduce some new trends in co-design and system acceleration.

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