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Fast, Efficient and Predictable Memory Accesses [electronic resource] : Optimization Algorithms for Memory Architecture Aware Compilation / by Lars Wehmeyer, Peter Marwedel.

By: Wehmeyer, Lars [author.]Contributor(s): Marwedel, Peter [author.] | SpringerLink (Online service)Material type: Text

TextLanguage: English Publisher: Dordrecht : Springer Netherlands, 2006Description: XI, 257 p. online resourceContent type: text Media type: computer Carrier type: online resourceISBN: 9781402048227Subject(s): Engineering | Computer science | Electronics | Systems engineering | Optical materials | Engineering | Circuits and Systems | Processor Architectures | Optical and Electronic Materials | Electronics and Microelectronics, InstrumentationAdditional physical formats: Printed edition:: No titleDDC classification: 621.3815 LOC classification: TK7888.4Online resources: Click here to access online

Contents:

Abstract -- Models and Tools -- Scratchpad Memory Optimizations -- Main Memory Optimizations -- Register File Optimization -- Summary -- Future Work.

In: Springer eBooksSummary: Fast, Efficient and Predictable Memory Accesses presents techniques for designing fast, energy-efficient and timing predictable memory systems. By using a careful combination of compiler optimizations and architectural improvements, we can achieve more than what would be feasible at one of the levels in isolation. The described optimization algorithms achieve the goals of high performance and low energy consumption. In addition to these benefits, the use of scratchpad memories significantly improves the timing predictability of the entire system, leading to tighter worst case execution time bounds (WCET). The WCET is a relevant design parameter for all timing critical systems. In addition, the book covers algorithms to exploit the power down modes of main memories in SDRAM technology, as well as the execute-in-place feature of Flash memories. The final chapter considers the impact of the register file, which is also part of the memory hierarchy.

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Abstract -- Models and Tools -- Scratchpad Memory Optimizations -- Main Memory Optimizations -- Register File Optimization -- Summary -- Future Work.

Fast, Efficient and Predictable Memory Accesses presents techniques for designing fast, energy-efficient and timing predictable memory systems. By using a careful combination of compiler optimizations and architectural improvements, we can achieve more than what would be feasible at one of the levels in isolation. The described optimization algorithms achieve the goals of high performance and low energy consumption. In addition to these benefits, the use of scratchpad memories significantly improves the timing predictability of the entire system, leading to tighter worst case execution time bounds (WCET). The WCET is a relevant design parameter for all timing critical systems. In addition, the book covers algorithms to exploit the power down modes of main memories in SDRAM technology, as well as the execute-in-place feature of Flash memories. The final chapter considers the impact of the register file, which is also part of the memory hierarchy.

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